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SEMICONDUCTOR TECHNICAL DATA
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1:10 LVCMOS Fanout Buffer
The MPC9120 is a 1:10 LVCMOS fanout buffer targeted to support Intel based Pentium IITM microprocessor chip sets. The device features 10 low skew outputs optimized to drive the clock inputs of standard unbuffered SO-DIMM SDRAM modules. Standard unbuffered SO-DIMM SDRAM modules require two clocks per module allowing for the device to drive up to four modules. The output buffers have been optimized to drive the load presented by the SDRAM module. The MPC9120 provides output shut off capabilities via an I2C serial port for applications which plan to use fewer than four modules and desire to minimize the power dissipation of the chip. Every output clock can be individually enabled/disabled through fields in the I2C control registers. After power up the default state is all outputs enabled. In applications where this default state is acceptable the I2C ports need not be exercised.
MPC9120
1:10 LVCMOS FANOUT BUFFER
* * * * * * *
Supports Intel PentiumTM and Pentium II Processor Architectures 10 Skew Controlled 3.3V Compatible SDRAM Clocks I2C Serial Bus Interface Extensive Output Enable Control Capability Space Efficient 28-Lead SSOP Package Operating Temperature Range of 0C to 70C 3.3V 5% Power Supply
SD SUFFIX 28-LEAD PLASTIC SSOP PACKAGE CASE 940E-02
VDD SDRAM0 SDRAM1 VSSO VDD SDRAM2 SDRAM3 VSS BUF_IN
1 2 3 4 5 6 7 8 9
28 VDD 27 SDRAM9 26 SDRAM8 25 VSS 24 VDD 23 SDRAM7 22 SDRAM6 21 VSS 20 OE 19 VDD 18 SDRAM5 17 VSS 16 VSSIIC 15 SCLOCK
FUNCTION TABLE
OE 0 1 V1, V2 High-Z 1x BUF_IN
VDD 10 SDRAM4 11 VSS 12 VDDIIC 13 SDATA 14
Figure 1. 28-Lead Pinout (Top View)
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice. 12/97
(c) Motorola, Inc. 1997
1
REV 0.2
MPC9120
SDRAM0 SDRAM1 SDRAM2 SDRAM3 SDRAM4 BUF_IN SDRAM5 SDRAM6 SDRAM7 SDRAM8 SDRAM9
SDATA SCLOCK
I2C INTERFACE
10
CONFIG REGISTERS
OE
Figure 2. Block Diagram
Table 1. Pin Descriptions
Pin Name BUF_IN SDRAM0:9 SDATA SCLK OE VDD VSS I/O I O I/O I I - - 3.3V CMOS clock input 3.3V CMOS SDRAM clock outputs Serial data for configuration control Serial clock input for configuration control. The state of the SDATA input is clocked into the device on the rising edge of this clock A Low forces all outputs into High-Z state 3.3V power supply connection Ground connection which should be connected directly to the ground plane Function
MOTOROLA
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TIMING SOLUTIONS BR1333 -- REV 5
MPC9120
I2C Interface The device has an I2C serial bus interface consisting of a serial clock input (SCLK) and a data line (SDATA) . The clock driver acts as a slave receiver on the I2C bus with a standard data transfer rate of up to 100 kbit/s. The MPC9120 is a `write only' device which will not respond to general call requests from the bus master. The I2C interface transfers data in byte length packets except for the start, stop and acknowledge bits. The clock driver supports block writes consisting of the following elements. 1) Start Bit 2) Address 3) Acknowledge Bit 4) Command Code 5) Acknowledge Bit 6) Byte Count 7) Acknowledge Bit 8) Data Fields (see Table 2) 9) Acknowledge Bit 10) Stop Bit Table 2. Serial Data Fields
Byte 0 Package Pin SDRAM6:9 1 Package Pin SDRAM4:5 2 Package Pin 18 11 N/A N/A N/A N/A N/A N/A 1. Not Used bits fields are "Don't Care" conditions. 2. When a bit field is programmed with a "1" (enable), the clock is active. A "0" (disable) means the clock is inactive. 27 SDRAM5 26 SDRAM4 23 Not Used 22 Not Used N/A Not Used N/A Not Used N/A Not Used N/A Not Used N/A SDRAM9 N/A SDRAM8 N/A SDRAM7 N/A SDRAM6 7 Not Used 6 Not Used 3 Not Used 2 Not Used Function SDRAM0:3 Bit 7 Not Used Bit 6 Not Used Bit 5 Not Used Bit 4 Not Used Bit 3 SDRAM3 Bit 2 SDRAM2 Bit 1 SDRAM1 Bit 0 SDRAM0
After each byte, the clock driver pulls down the data line to acknowledge the transfer. The clock driver holds SDATA low during the high state of SCLK. The 7-bit address of the clock driver is: A7 1 A6 1 A5 0 A4 1 A3 0 A2 0 A1 1 R/W 0
Note: A7 is the first address bit
The `Command Code' should be set to all `0's and the `Byte Count' can range from 1 to 3. The data fields are transferred sequentially in ascending order starting with Byte 0 - Configuration Function. The MPC9120 is compliant with the DC/AC characteristics of a "Standard-Mode" I2C bus device. The logic thresholds are dependent on the 3.3V supply. For additional information on the I2C bus, refer to the document, 3114 - "The I 2 C-bus and how to use it (including specifications)" available from Philips Semiconductors: http://www.semiconductors.philips.com
MAXIMUM RATINGS*
Symbol VDD Tstg VIH VIL ESD 3.3V Core Supply Voltage Storage Temperature Range 3.3V Input High Voltage (Note 3.) 3.3V Input Low Voltage ESD Input Protection Parameter Min -0.5 -65 -0.5 -0.5 2000 Max 4.6 150 4.6 Unit V C V V V
* Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. 3. VIH should not exceed VDD level.
TIMING SOLUTIONS BR1333 -- REV 5
3
MOTOROLA
MPC9120
DC CHARACTERISTICS (VDD = 3.3V 5%; GND = 0.0V; TA = 0 to +70C; Unless Otherwise Specified)
Symbol IDD Characteristic Supply Current for VDD No Clock Mode Active 66MHz Active 100MHz -0.3 2.0 -5.0 Min Typ Max 3 230 360 0.8 VDD+0.3 5 0.40 2.4 TBD TBD Unit mA Condition BUF_IN = VSS or VDD
VIL VIH IIL VOL VOH CI LI
Input Low Voltage Input High Voltage Input Leakage Current 3.3V Output Low Voltage 3.3V Output High Voltage Input Capacitance Input Inductance
V V A V V pF nH 0 < VIN < VCC/VCCI IOL = 1mA IOH = -1.0mA Except XTL_In, XTL_Out Except XTL_In, XTL_Out
AC CHARACTERISTICS (VDD = 3.3V 5%; GND = 0.0V; TA = 0 to +70C; Unless Otherwise Specified)
Symbol Characteristic Min Typ Max Unit Condition SDRAM Clock Outputs (SDRAM0:17) tsk dt tp tVIH tVIL trise tfall tPLH tPHL tPZL, tPZH Output Clock Skew Output Duty Cycle Clock Period High Time Low Time Rise Time Fall Time Low to High Propagation Delay High to Low Propagation Delay Enable Delay 66MHz 100MHz 66MHz 100MHz 66MHz 100MHz 45 15.0 10.0 5.6 3.3 5.3 3.1 1.5 1.5 1.0 1.0 1.0 1.0 4.0 4.0 5.0 5.0 8.0 8.0 250 55 15.5 10.5 ps % ns ns ns V/ns V/ns ns ns ns ns Note 4. Note 5. Note 4. Measured at 2.4V Measured at 0.4V From 0.4V to 2.4V From 2.4V to 0.4V
tPLZ, Disable Delay tPHZ 4. Measured on the rising edge of the clock at 1.5V. 5. Input slew rate >1V/ns.
MOTOROLA
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TIMING SOLUTIONS BR1333 -- REV 5
MPC9120
APPLICATIONS INFORMATION
Output Series Termination With typical MPC9120 edge rates of 1.5V/ns, a PCB trace becomes a transmission line when it is over 1-inch in length. This transmission line needs some sort of termination scheme to ensure good signal integrity at the load (device receiving clock signal). Most motherboards use the practice of series termination. In series termination, a series termination resistor (external resistor) is added in series with the driver device output, as shown in Figure 3, series termination resistor value is chosen so that its value, added to the output impedance of the driver, is equal to the PCB trace impedance, or in other words, RTH = RS + ZL . The series termination resistor must be located close to the device output. Typical system PCB trace impedance is 50-70, which is low enough to produce sufficient signal rise and fall time at the load capacitance presented by a standard CMOS input. Figure 4 illustrates proper series termination of the 15 MPC9120 output driving a 60 transmission line.
RTH
RS Series Termination Resistor
ZL Transmission Line (PCB Clock Trace)
Output Buffer Model
Figure 3. Clock Output Series Termination
15
45 Series Termination Resistor
60 Transmission Line (PCB Clock Trace)
Output Buffer Model
Figure 4. Clock Output Series Termination
Pull-Up Voltage (V) 0 1.000 1.400 1.500 1.650 1.800 2.000 2.400 2.600 3.135 3.300 3.465 Imin (mA) -72 -72 -68 -67 -64 -60 -54 -39 -30 0 - - Ityp (mA) -116 -116 -110 -107 -103 -98 -90 -69 -56 -15 0 - Imax (mA) -198 -198 -188 -184 -177 -170 -157 -126 -107 -46 -23 0 Voltage (V) 0 0.400 0.650 0.850 1.000 1.400 1.500 1.650 1.800 1.950 3.315 3.600 Imin (mA) 0 23 35 43 49 61 64 67 70 72 72 -
Pull-Down Ityp (mA) 0 34 52 65 74 93 98 103 108 112 112 112 Imax (mA) 0 53 83 104 118 152 159 168 177 184 204 204
Figure 5. Typical Output V/I Characteristics for MPC9120
TIMING SOLUTIONS BR1333 -- REV 5
5
MOTOROLA
MPC9120
OUTLINE DIMENSIONS
SD SUFFIX PLASTIC SSOP PACKAGE CASE 940E-02 ISSUE A
28X
K REF 0.12 (0.005)
M
TU
S
V
S
K L/2 L
PIN 1 IDENT 1 14 28 15
J B
J1
K1
SECTION N-N
A -V- 0.20 (0.008)
M
-U- N
0.25 (0.010)
TU
S
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION/INTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF K DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR INTRUSION SHALL NOT REDUCE DIMENSION K BY MORE THAN 0.07 (0.002) AT LEAST MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 10.07 10.33 5.20 5.38 1.73 1.99 0.05 0.21 0.63 0.95 0.65 BSC 0.47 0.63 0.09 0.20 0.09 0.16 0.25 0.38 0.25 0.33 7.65 7.90 0_ 8_ INCHES MIN MAX 0.396 0.406 0.205 0.212 0.068 0.078 0.002 0.008 0.024 0.037 0.026 BSC 0.018 0.024 0.003 0.008 0.003 0.006 0.010 0.015 0.010 0.013 0.301 0.311 0_ 8_
N F DETAIL E C D G H -W-
0.076 (0.003) -T-
SEATING PLANE
DETAIL E
Pentium and Pentium II are trademarks of Intel Corp. Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
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MPC9120/D TIMING SOLUTIONS BR1333 -- REV 5

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